Focus Areas
My current research projects fall broadly under the three areas listed
below. My research group's activities have been funded via
government (NSF, LLNL, NSA, NCMR, DNDO) as well as industrial (Intel,
Nascentric, NSC, SRC, Accelicon, NVIDIA) sources.
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Some of the papers listed under the links on this page may appear in
multiple links, based on their topics.
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Computer Systems: In this category, my work falls into two
subcategories.
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The first is computer architecture from the circuits up
(including the design of efficient NoCs using a resonant clocking as well
as a superposition-of-sinusoids paradigm, special function units for
comparison, hashing, logarithm/antilogarithm computation, cryptographic
key generation, Boolean Satisfiability and sorting, low energy and low
power design using sub-threshold circuits, system prototyping, specialized
architectures for arithmetic circuits, radiation tolerance/detection, as
well as circuit and architectural approaches for resilience, crosstalk avoidance, clocking,
leakage reduction and testability. My group also develops system prototypes
to validate our ideas - for example, in extreme low power/energy
computation, architectures for cryptography and FPGA based architectures
for Boolean Satisfiability).
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The second sub-category consists of algorithm
acceleration (using GPUs, FPGAs and custom ICs), for algorithms in the VLSI
CAD (for fault simulation, logic simulation, circuit simulation, fault
table generation, SAT), radar signal processing (for weather radar),
cryptography and communications (LDPC decoders, MIMO decoders, WiMAX
decoders) domains.
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Logic and its applications: In this area, my work initially started
in the space of logic synthesis for VLSI CAD. In the last couple of years,
I have directed this work towards genomics (predictor inference, Gene
Regulatory Network (GRN) construction, determining optimal drug regime for
a genetic disease), noise based logics and their realization, and Boolean
Satisfiability solvers (using noise based logic as well as GPU, FPGA and
custom IC based accelerators).
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Interdisciplinary extensions: The above two areas form a
spring-board from which I engage in research in other domains. I explore
extensions of the above two areas to other areas such as IP routing
(routing table compression, architecture and design of Ternary CAMs),
Digital Signal Processing (architectures and designs for FFT, FPGA and GPU
based radar signal processors), optical networking (SAT based Routing and
Wavelength Assignment for DWDM optical networks), wireless communication
(MIMO decoders, WiMAX decoders) and coding (LDPC decoders, fix-free code
generators).
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