Microprocessor System Design

This page is under construction...

    Instructors:
    A.L. Narasimha Reddy, email:reddy at ece dot tamu dot edu, phone:845-7598
    Sunil P Khatri, email:i r t a h k l i n u s (spell backwards, drop spaces) at tamu dot edu, phone:845-8371
    Class Hours:
    Monday, Wednesday, Friday 1:50pm - 2:40pm, Zachry 223C.
    Lab Hours:
    Section 501: Monday, 3:00pm - 5:50pm, Zachry 115D.
    Section 502: Tuesday, 2:20pm - 5:10pm, Zachry 115D.
    Section 503: Wednesday, 3:00pm - 5:50pm, Zachry 115D.
    Office hours:
    Reddy Wed 4pm - 5pm
    Reddy Thu 9am - 10am
    Khatri Thu 9am - 10am
    Khatri Wed 10am - 11am
    Class Room:
    223C Zachry
    Graduate Assistant:
    Rajesh Garg (rajeshgarg at tamu dot edu)
    Office hours: Thursday 3pm - 4pm in the lab (Zachry 115D)
    Class mailing list is ecen449fall07@listserv.tamu.edu
    Resources:
  1. Virtex-II Pro Development System
    Xilinx XUP Virtex-II Pro Development System
    Digilent Inc. Virtex-II Pro Development System
    XUPV2P User Guide
    EDK8.2i Reference Manual
    ISE8.2i Quick Start Manual
  2. Logic Analyzer and Oscilloscope
    Agilent 1673G Logic Analyzer
    Agilent 54622D Mixed Signal Oscilloscope
  3. Linux Documentation (for Lab 4)
    Dr. John Kelm's write up
    O'Reilly's Linux Device Drivers, 2nd Edition
  4. Video Decoder Documentation (for Lab 5)
    ADV7183B Video Decoder manual
    Digilent Video Decoder Board(VDEC1) Reference Manual
  5. Verilog Documentation
    Verilog Quick Reference
    Verilog Reference Card
    Longer Verilog Reference
    Nonblocking and Blocking Assignments in Synthesizable Verilog
  6. Class Notes:
    Posted here on this web page. The notes are either developed by the course instructors or derived from other original copyrighted classnotes.
    Grading policy:
    Homeworks 10%, Lab 50% (5% per week), Test1 (2 hours) 20%, Test2 (2 hours) 20%
    EE449 will be graded on a curve.
    Course Objective:
    The goal of this course is to provide the student with an in-depth knowledge of digital circuit design using an embedded platform as an implementation method. We will cover hardware and software co-design, using a commercial FPGA with an embedded on-chip microprocessor.
    At the end of the course the student should be able to view the design of digital systems from a embedded hardware/software perspective and obtain a set of fundamental concepts and design skills that can be applied to a wide variety of digital design problems.
    Important Logistical Issues:
    As indicated in the first week of class, you are responsible to read this page and familiarize yourself with the important logistical information on it.
    Please remember that email will be used as an official means of communicating class information to you. You should make sure that the email address that you gave on the first day of class is a current and functioning address. In case of any changes in your email address, please let one of us know ASAP.
    Per University Regulations, we will allow a student who is absent from class for the observance of a religious holy day to take an examination or complete an assignment scheduled for that day within a reasonable time after the absence, if, not later than the 15th day after the first day of the semester, the student notifies one of us that they would be absent on which particular days.
    If you believe that you have a disability requiring an accomodation, the University provides academic adjustments and auxiliary aids as defined under the law. In such a case, you should register your documentation with the Office of Services for Students with Disabilities before any accomodations are made. Once this office reviews your documentation and verifies your condition, we will make reasonable accomodations.
    Remember that plagiarism will not be tolerated and will be dealt with under the Aggie Honor System Office guidelines.
Tentative Schedule -subject to change
Week Monday Topic Wednesday Topic Friday Topic Laboratory Comments
1 (8/27, 8/29, 8/31) Course Overview (Khatri) FPGAs and Reconfigurable computing (Khatri) FPGAs and Reconfigurable computing (Khatri) Login, meet TA, Scope+LSA usage HW1 out 8/31, due 9/17 HW1 Solutions
2 (9/3, 9/5, 9/7) Verilog (Khatri) Verilog (Khatri) Verilog (Khatri) Introduction
Lab 1 - hardware
3 (9/10, 9/12, 9/14) C Programming (Reddy) C Programming (Reddy) C Programming (Reddy) Lab 2 - software
4 (9/17, 9/19, 9/21) ARM Guest lecture (Reddy) Hardware-Software communication (Reddy) Xilinx framework (Khatri) Lab 2 - software HW2 out 9/21, due 10/5 HW2 Solutions
5 (9/24, 9/26, 9/28) Hardware Software codesign (Reddy) Hardware Software codesign (Reddy) Hardware Software codesign (Reddy) Lab 3 - hardware/software
6 (10/1, 10/3, 10/5 Linux for Hardware Development (Reddy) Linux for Hardware Development (Reddy) Some tips on programming (Reddy) Lab 4.1
7 (10/8, 10/10, 10/12 Review (Khatri) Review (Reddy) TBA Lab 4.2
    TEST 1 on THU 10/11, Location ZEC 223C, Time 7pm - 9pm
8 (10/15, 10/17, 10/19 Device Drivers (Reddy) Device Drivers (Reddy) Device Drivers (Reddy) Lab 4.3
9 (10/22, 10/24, 10/26 Realtime Issues (Reddy) Realtime Issues (Reddy) TBA Lab 4.4
my_music.h
HW3 out 10/26, due 11/9 HW3 Solutions
10 (10/29, 10/31, 11/2 The Design Process (Khatri) Display formats and conversions (Reddy) TBA Lab 5.1
11 (11/5, 11/7, 11/9 Pulse modulation (Khatri) Pulse modulation (Khatri) TBA Lab 5.2
lab5_c.zip
12 (11/12, 11/14, 11/16 Different Memories (Reddy) Transmission lines (Khatri) TBA Lab 5.3 HW4 out 11/12, due 11/26 HW4 Solutions
13 (11/19, 11/21, 11/23 Transmission lines (Khatri) TBD TBD Lab 5.4 - TBA
14 (11/26, 11/28, 11/30 Review Review Review Lab 5 - bonus week
    TEST 2 on THU 11/29, Location TBA, Time 7pm - 9pm