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Supervised students/post-docs are delineated with an asterisk (*).

 

 

Recent Publications

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[AICSP’12] *Suming Lai and Peng Li, “A fully on-chip area-efficient CMOS low-dropout regulator with fast load regulation,” Analog Integrated Circuits and Signal Processing (to appear). 

 

[ISQED’12] *Yongtae Kim and Peng Li, “An ultra-Low voltage digitally controlled low-dropout regulator with digital background calibration,” in Proc. of IEEE Symp. on Quality Electronic Design, March 2012 (to appear).

 

[ISQED’12] *Tong Xu and Peng Li, “Design and optimization of power gating for DVFS applications,” in Proc. of IEEE Symp. on Quality Electronic Design, March 2012 (to appear).

 

[PLoS One’11] *Boyuan Yan and Peng Li, “An integrative view of mechanisms underlying generalized spike-and-wave epileptic seizures and its implication on optimal therapeutic treatments,” PLoS One 6(7): e22440. doi:10.1371/journal.pone.0022440 (impact factor 4.441, July 2011, 20 pages).

 

[IJCNN’11] *Mingchao Wang, *Boyuan Yan, *Jingzhen Hu and Peng Li, “Large-scale simulation of neural networks with biophysically accurate models on graphics processors,” IEEE International Joint Conference on Neural Networks, pp. 3184-3193, July 2011.

 

[TVLSI’11] Zhuo Feng, *Zhiyu Zeng and Peng Li, “Parallel on-chip power distribution network analysis on multi-core-multi-GPU platforms,” in IEEE Trans. on Very Large Scale Integration Systems, vol. 19, no. 10, pp. 1823-1836, October 2011.

 

[DAC’11] *Parijat Mukherjee, Peter Fang, Rod Burt, and Peng Li, “Automatic stability checking for large linear analog integrated circuits,” IEEE/ACM Design Automation Conference, pp. 304-309, June 2011 (acceptance rate 22.6%) (Best paper award, 1 out of 690 submissions, <1%).

 

[DAC’11] *Tong Xu, Peng Li and *Boyuan Yan, “Decoupling for power gating: sources of power noise and design strategies,” IEEE/ACM Design Automation Conference, pp. 1002-1007, June 2011 (acceptance rate 22.6%).

 

[DAC’11] *Leyi Yin, *Yongtae Kim and Peng Li “High effective-resolution built-in jitter characterization with quantization noise shaping,” IEEE/ACM Design Automation Conference, pp. 765-770, June 2011 (acceptance rate 22.6%).

 

[TCAS’11] Yenpo Ho, Garng M. Huang and Peng Li, “Dynamical properties and design analysis for nonvolatile memristor memories,” in IEEE Trans. on Circuits and Systems I: Fundamental Theory and Applications, vol. 58, no. 4, pp. 724-736, April 2011.

 

 

 

Refereed Journal Articles

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[J34] [AICSP’12] *Suming Lai and Peng Li, “A fully on-chip area-efficient CMOS low-dropout regulator with fast load regulation,” Analog Integrated Circuits and Signal Processing (to appear). 

 

[J33] [JCP’12] *Haokai Lu and Peng Li, “Stochastic projective methods for simulating stiff chemical reacting systems,” Journal of Computational Physics (to appear). 

 

[J32] [TCBB’11] *Yong Zhang, Peng Li and Garng M. Huang, “Quantifying dynamic stability of genetic memory circuits,” IEEE/ACM Transactions on Computational Biology and Bioinformatics (to appear).

 

[J31] [TODAES’11] *Wei Dong and Peng Li, “Parallel circuit simulation with adaptively controlled projective integration,” in ACM Trans. on Design Automation of Electronic Systems, vol. 16, no.4, October 2011.

 

[J30] [PLoS One’11] *Boyuan Yan and Peng Li, “An integrative view of mechanisms underlying generalized spike-and-wave epileptic seizures and its implication on optimal therapeutic treatments,” PLoS One 6(7): e22440. doi:10.1371/journal.pone.0022440 (impact factor 4.441, July 2011, 20 pages).

 

[J29] [TVLSI’11] Zhuo Feng, *Zhiyu Zeng and Peng Li, “Parallel on-chip power distribution network analysis on multi-core-multi-GPU platforms,” in IEEE Trans. on Very Large Scale Integration Systems, vol. 19, no. 10, pp. 1823-1836, October 2011.

 

[J28] [TODAES’11] *Zhiyu Zeng, Zhuo Feng, Peng Li and Vivek Sarin, “Locality-driven parallel static analysis for power delivery networks,” in ACM Trans. on Design Automation of Electronic Systems, 16, 3, Article 28, 17 pages, June 2011.

 

[J27] [TCAS’11] Yenpo Ho, Garng M. Huang and Peng Li, “Dynamical properties and design analysis for nonvolatile memristor memories,” in IEEE Trans. on Circuits and Systems I: Fundamental Theory and Applications, vol. 58, no. 4, pp. 724-736, April 2011.

 

[J26] [TCAD’11] *Guo Yu and Peng Li, “Hierarchical analog/mixed-signal circuit optimization under process variations and tuning,” in IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 30, no. 2, pp. 313-317, February, 2011.

 

[J25] [JCNS’11] *Boyuan Yan and Peng Li, “Reduced order modeling of passive and quasi-active dendrites for nervous system simulation,” Journal of Computational Neuroscience, 25 pages, January 2011.

 

[J24] [TCAD’11] *Xaioji Ye, *Wei Dong, Peng Li and Sani Nassif, “Hierarchical multialgorithm parallel circuit simulation,” in IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 30, issue 1, pp. 45-58,  January 2011.

    

[J23] [TCAD’10] *Xaioji Ye, Peng Li, Min Zhao, Rajendran Panda and Jiang Hu, “Analysis of large clock meshes via harmonic-weighted model order reduction and port sliding,” in IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems , vol. 29, no. 9, pp. 1342-1353, September 2010 (TCAD best paper award nomination).

 

[J22] [TVLSI’10] Rupak Samanta, Jiang Hu and Peng Li, “Discrete buffer and wire sizing for link-based non-tree clock networks,” in IEEE Trans. on Very Large Scale Integration Systems, vol. 18, no. 7, pp. 1025 – 1035, July 2010.

 

[J21] [JLPE’10] *Akshit Dayal, Peng Li and Garng M. Huang, “Robust SRAM design via joint sizing and voltage optimization under dynamic stability constraints,” in Journal of Low Power Electronics, vol. 6, no. 1, Apr. 2010.

 

[J20] [JLPE’10] *Guo Yu and Peng Li, “Exploring circuit adaptation for yield optimization of low-power all-digital PLLs,” Journal of Low Power Electronics, vol. 6, no. 1, Apr. 2010.

 

[J19] [TCAS’10] *Xiaoji Ye, Peng Li and Frank Liu, “Exact time-domain second-order adjoint sensitivity computation for linear circuit analysis and optimization,” in IEEE Trans. on Circuits and Systems I: Fundamental Theory and Applications, vol. 57, no. 1, pp. 236-248, January 2010.

 

[J18] [TVLSI’09] Ganesh Venkataraman, *Zhuo Feng, Jiang Hu, Peng Li, “Combinatorial algorithms for fast clock mesh optimization,” in IEEE Trans. on Very Large Scale Integration Systems, vol. 18, no. 1, pp. 131-141, Jan. 2010.

 

[J17] [IET’09] *Zhuo Feng, Peng Li and Zhuoxiang Ren, “SICE: design-dependent statistical interconnect corner extraction under inter/intra-die variations,” IET Circuits, Devices & Systems, vol. 3, iss. 5, pp. 248-258, 2009.

 

[J16] [TCAD’09] *Zhiyu Zeng and Peng Li, “Locality-driven parallel power grid optimization,” in IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 8, pp. 1190-1200, August 2009.

 

[J15] [TCAD’09] *Wei Dong and Peng Li, “A parallel harmonic balance approach to steady-state and envelope-following simulation of driven and autonomous circuits,” in IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 4, pp. 490-501, April 2009.

 

[J14] [TCAD’09] *Zhuo Feng, Peng Li and Yaping Zhan, “An on-the-fly parameter dimension reduction approach to fast second-order statistical static timing analysis,” in IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 28,  no. 1,  pp. 141-153, January 2009.


[J13] [TVLSI’09] *Zhuo Feng and Peng Li, “Performance-oriented parameter dimension reduction of VLSI circuits,” in IEEE Trans. on Very Large Scale Integration Systems, vol. 17, no. 1, pp. 137-150, January 2009.


[J12] [TCAD’08] Yang Yi, Peng Li, Vivek Sarin and Weiping Shi, "A preconditioned hierarchical algorithm for impedance extraction of three-dimensional structures with multiple dielectrics," in IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 27,  no. 11,  pp. 1918-1927, November 2008.

 

[J11] [TCAD’08] *Guo Yu, *Wei Dong, *Zhuo Feng and Peng Li, “Statistical static timing analysis considering process variation model uncertainty,” in IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 10, pp. 1880-1890, Oct. 2008.


[J10] [TCAD’07] *Wei Dong and Peng Li, “Hierarchical harmonic balance methods for frequency-domain analog circuits analysis,” in IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 12, pp. 2089-2101, December. 2007.

  
[J9] [TVLSI’07] Peng Li, *Zhuo Feng and Emrah Acar, “Characterizing multi-stage nonlinear drivers and variability for accurate timing and noise analysis,” in IEEE Trans. on Very Large Scale Integration Systems, vol. 15, no. 11, pp. 1205-1214, November 2007.

   
[J8] [TCAS’07] *Guo Yu and Peng Li, “Efficient lookup table based modeling for robust design of Sigma-Delta ADCs,” in IEEE Trans. on Circuits and Systems I: Fundamental Theory and Applications, vol. 54, no. 7, pp. 1513-1528, July 2007.


[J7] [TVLSI’07] Shiyan Hu, Qiuyang Li, Jiang Hu and Peng Li, “Utilizing redundancy for timing critical interconnect,” in IEEE Trans. on Very Large Scale Integration Systems, vol. 15, no. 10, pp. 1067-1080, October 2007. 


[J6] [TVLSI’07] *Xiaoji Ye, Frank Liu, and Peng Li, “Fast variational interconnect delay and slew computation using quadratic models,” in IEEE Trans. on Very Large Scale Integration Systems, vol. 15, no. 8, pp. 913-926, August 2007.


[J5] [TCAD’06] Peng Li, “Statistical sampling-based parametric analysis of power grids,” in IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 12, pp. 2852-2867, December 2006. 


[J4] [TCAD’06] Peng Li, Lawrence Pileggi, Mehdi Asheghi and Rajit Chandra, “IC thermal simulation and modeling via efficient multigrid-based techniques,” in IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 9, pp. 1763-1776,  September, 2006.  


[J3] [JLOPE’06] Yangdong Deng and Peng Li, “Temperature-aware floorplanning of 3-D ICs considering thermally dependent leakage power,” Journal of Low Power Electronics, vol. 2, no.2, August 2006.


[J2] [TCAD’05] Peng Li and Lawrence Pileggi, “Compact reduced-order modeling of weakly nonlinear analog and RF circuits,” in IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 2, pp. 184-203, Feb, 2005 (The most downloaded IEEE TCAD publication in 2005).


[J1] [TCAD’03] Peng Li and Lawrence Pileggi, “Efficient per-nonlinearity distortion analysis for analog and RF circuits,” in IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 10, pp. 1297-1309, October 2003.

 

Refereed Conference Publications

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[C85] [ISQED’12] *Yongtae Kim and Peng Li, “An ultra-Low voltage digitally controlled low-dropout regulator with digital background calibration,” in Proc. of IEEE Symp. on Quality Electronic Design, March 2012 (to appear).

 

[C84] [ISQED’12] *Tong Xu and Peng Li, “Design and optimization of power gating for DVFS applications,” in Proc. of IEEE Symp. on Quality Electronic Design, March 2012 (to appear).

 

[C83] [ICCAD’11] *Zhiyu Zeng, *Tong Xu, Zhuo Feng and Peng Li, “Fast static analysis of power grids: algorithms and implementations,” in Proc. of IEEE/ACM Int. Conf. on Computer-Aided Design, pp. 488-493, November 2011 (invited).

 

[C82] [IJCNN’11] *Mingchao Wang, *Boyuan Yan, *Jingzhen Hu and Peng Li, “Large-scale simulation of neural networks with biophysically accurate models on graphics processors,” IEEE International Joint Conference on Neural Networks, pp. 3184-3193, July 2011.

 

[C81] [DAC’11] *Parijat Mukherjee, Peter Fang, Rod Burt, and Peng Li, “Automatic stability checking for large linear analog integrated circuits,” IEEE/ACM Design Automation Conference, pp. 304-309, June 2011 (acceptance rate 22.6%) (Best paper award, 1 out of 690 submissions, <1%).

 

[C80] [DAC’11] *Tong Xu, Peng Li and *Boyuan Yan, “Decoupling for power gating: sources of power noise and design strategies,” IEEE/ACM Design Automation Conference, pp. 1002-1007, June 2011 (acceptance rate 22.6%).

 

[C79] [DAC’11] *Leyi Yin, *Yongtae Kim and Peng Li “High effective-resolution built-in jitter characterization with quantization noise shaping,” IEEE/ACM Design Automation Conference, pp. 765-770, June 2011 (acceptance rate 22.6%).

 

[C78] [TAU’11] *Tong Xu, Peng Li and *Boyuan Yan, “Decoupling strategies for reducing power gating induced supply noise,” in Proc. of ACM Int. Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, March 2011.

 

[C77] [ISQED’11] *Leyi Yin and Peng Li, “RF BIST for ADPLL-based polar transmitters with wide-band DCO gain calibration,” in Proc. of IEEE Int. Symp. on Quality Electronic Design, pp. 303-340, March 2011.

 

[C76] [ISQED’11] *Zhiyu Zeng, Zhuo Feng and Peng Li, “Efficient checking of power delivery integrity for power gating,” in Proc. of IEEE Int. Symp. on Quality Electronic Design, pp. 663-670, March 2011.

 

[C75] [ICCAD’10] *Xiaoji Ye and Peng Li, “On-the-fly runtime adaptation for efficient execution of parallel multi-algorithm circuit simulation,” in Proc. of IEEE/ACM Int. Conf. on Computer-Aided Design, pp. 298-304, November 2010 (acceptance rate 30%).

 

[C74] [ICCAD’10] *Amandeep Singh and Peng Li, “On behavioral model equivalence checking for large analog/mixed signal systems,” in Proc. of IEEE/ACM Int. Conf. on Computer-Aided Design, pp. 55-61, November 2010 (acceptance rate 30%).

 

[C73] [ICCAD’10] Zhuo Feng and Peng Li, “Fast thermal analysis on GPU for 3D-ICs with integrated microchannel cooling,” in Proc. of IEEE/ACM Int. Conf. on Computer-Aided Design, pp. 551-555, November 2010 (acceptance rate 30%).

 

[C72] [ICCCAS’10] Yenpo Ho, Garng M. Huang and Peng Li, “Memristor system properties and its design applications to circuits such as nonvolatile memristor memories,” in Proc. of IEEE Int. Conf. on Communications, Circuits and Systems, pp. 805-819, July 2010 (invited).

 

[C71] [DAC’10] *Leyi Yin and Peng Li, “Exploiting reconfigurability for low-cost in-situ test and monitoring of digital PLLs,” in Proc. of ACM/IEEE Design Automation Conf., pp. 929-934, June 2010 (acceptance rate 24.4%).

 

[C70] [DAC’10] *Zhiyu. Zeng, *Xiaoji Ye, Zhuo Feng and Peng Li, “Tradeoff analysis and optimization of power delivery networks with on-chip voltage regulation,” in Proc. of ACM/IEEE Design Automation Conf., pp. 831-836, June 2010 (acceptance rate 24.4%).

 

[C69] [DAC’10] *Xiaoji Ye and Peng Li, “Parallel program performance modeling for runtime optimization of multi-algorithm circuit simulation,” in Proc. of ACM/IEEE Design Automation Conf., pp. 561-566, June 2010 (acceptance rate 24.4%).

 

[C68] [DAC’10] *Yong Zhang, Peng Li and Garng M. Huang, “Separatrices in high-dimensional state space: system-theoretical tangent computation and application to SRAM dynamic stability analysis,” pp. 567-572, in Proc. of ACM/IEEE Design Automation Conf., June 2010 (acceptance rate 24.4%).

 

[C67] [TAU’10] *Xiaoji Ye and Peng Li, “Performance modeling of a hierarchical multi-algorithm parallel circuit simulator,” in Proc. of ACM Int. Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, March 2010 (acceptance rate 50%).

 

[C66] [ISPD’10] Venkata Rajesh Mekala, Yifang Liu, *Xiaoji Ye, Jiang Hu and Peng Li, “Accurate clock mesh sizing via sequential quadratic programming,” in Proc. of ACM Int. Symp. on Physical Design, March 2010.

 

[C65] [ICCAD’09] *Yong Zhang and Peng Li, “Gene-regulatory memories: electrical-equivalent modeling, simulation and parameter identification,” in Proc. of IEEE/ACM Int. Conf. on Computer-Aided Design, pp. 491-496, November 2009 (acceptance rate 26.3%).

 

[C64] [ICCAD’09] *Wei Dong and Peng Li, “Final-value ODEs: stable numerical integration and its application to parallel circuit analysis,” in Proc. of IEEE/ACM Int. Conf. on Computer-Aided Design, pp. 403-409, November 2009 (acceptance rate 26.3%).

 

[C63] [ICCAD’09] *Xiaoji Ye, *Srinath S. Narasimhan and Peng Li, “Leveraging efficient parallel pattern search for clock mesh optimization,” in Proc. of IEEE/ACM Int. Conf. on Computer-Aided Design, pp. 529-534, November 2009 (acceptance rate 26.3%).

 

[C62] [ICCAD’09] Yenpo Ho, Garng M. Huang and Peng Li, “Nonvolatile memristor memory: device characteristics and design implications,” in Proc. of IEEE/ACM Int. Conf. on Computer-Aided Design, pp. 485-490, November 2009 (acceptance rate 26.3%).

 

[C61] [DAC’09] *Wei Dong and Peng Li, “Parallelizable stable explicit numerical integration for efficient circuit simulation,” in Proc. of IEEE/ACM Design Automation Conf., pp. 382-385, July 2009 (acceptance rate 21.7%).

 

[C60] [ISQED’09] *Zhiyu Zeng, Peng Li and *Zhuo Feng, “Parallel partitioning based on-chip power distribution network analysis using locality acceleration,” in Proc. of IEEE Int. Symp. on Quality Electronic Design, pp. 776-781, March 2009 (acceptance rate 29.0%).

 

[C59] [ISQED’09] *Xiaoji Ye and Peng Li, “An application-specific adjoint sensitivity analysis framework for clock mesh sensitivity computation,” in Proc. of IEEE Int. Symp. on Quality Electronic Design, pp. 634-640, March 2009 (acceptance rate 29.0%).

 

[C58] [FPGA’09] Kanupriya Gulati, Sunil P. Khatri and Peng Li, “Closed-loop modeling of power and temperature profiles of FPGAs,” ACM/SIGDA Int. Symp. on Field-Programmable Gate Arrays, 9 pages, February 2009.

 

[C57] [ICCAD’08 ] Zhuo Feng and Peng Li, "Multigrid on GPU: tackling power grid analysis on parallel SIMT platforms,” in Proc. of IEEE/ACM Int. Conf. on Computer-Aided Design, pp. 647-654, November 2008, (acceptance rate 26.6%), 
(Best paper award nomination, 14 out of 458 submissions, 3%).

 

[C56] [ICCAD’08] *Wei Dong, Peng Li and Garng M. Huang, “SRAM dynamic stability: theory, variability and analysis,” in Proc. of IEEE/ACM Int. Conf. on Computer-Aided Design, pp. 378-385, November 2008 (acceptance rate 26.6%)
(Best paper award nomination, 14 out of 458 submissions, 3%).

 

[C55] [ICCAD’08] *Guo Yu and Peng Li, “Yield-aware hierarchical optimization of large analog integrated circuits,” in Proc. of IEEE/ACM Int. Conf. on Computer-Aided Design, pp. 79-84, November 2008 (acceptance rate 26.6%).

 

[C54] [ICCAD’08] *Xiaoji Ye, *Wei Dong, Peng Li and Sani R. Nassif, “MAPS: multi-algorithm parallel circuit simulation,” in Proc. of IEEE/ACM Int. Conf. on Computer-Aided Design, pp. 73-78, November 2008 (acceptance rate 26.6%).

 

[C53] [DAC’08] *Wei Dong, Peng Li and *Xiaoji Ye, “WavePipe: parallel transient simulation of analog and digital circuits on multi-core shared-memory machines,” in Proc. of IEEE/ACM Design Automation Conf., pp. 238-243, June 2008 (acceptance rate 23.0%), ( Best paper award, two out of 639 submissions, 0.3%).

 

[C52] [ISCAS’08] Rajesh Garg, Peng Li and Sunil P. Khatri “Modeling dynamic stability of SRAMs in the presence of single event upsets (SEUs)”, in Proc. of IEEE Int. Symp. on Circuits and Systems, pp. 1788-1791, May 2008.

 

[C51] [ISPD’08] Rupak Samanta, Jiang Hu and Peng Li, “Discrete buffer and wire sizing for link-based non-tree clock networks,” ACM Int. Symp. on Physical Design, pp. 175-181, April 2008.

 

[C50] [ICCDCS’08] Ivick Guerra-Gomez, Esteban Tlelo-Cuautle, Peng Li, and Georges Gielen, “Simulation-based optimization of UGCs performances”, in Proc. of the 7th IEEE International Caribbean Conference on Devices, Circuits  and Systems, pp. 1-4, April 2008.

 

[C49] [ISQED’08] *Xiaoji Ye, Min Zhao, Rajendran Panda, Peng Li and Jiang Hu, “Accelerating clock mesh simulation using matrix-level macromodels and dynamic time step rounding,” in Proc. of IEEE Int. Symp. on Quality Electronic Design, pp. 627-632, March 2008 (acceptance rate 30%).

 

[48] [TAU’08] *Xiaoji Ye, *Wei Dong and Peng Li, “A multi-algorithm approach to parallel circuit simulation,” in Proc. of ACM/IEEE Int. Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, February 2008.

 

[C47] [ICCAD’07] *Zhuo Feng and Peng Li, “A methodology for timing model characterization for statistical static timing analysis,” in Proc. of IEEE/ACM Int. Conf. on Computer-Aided Design, pp. 725-729, November 2007 (acceptance rate 27.3%).

 

[C46] [ICCAD’07] *Xiaoji Ye, Peng Li, Min Zhao, Rajendran Panda and Jiang Hu, “Analysis of large clock meshes via harmonic-weighted model order reduction and port sliding,” in Proc. of IEEE/ACM Int. Conf. on Computer-Aided Design, pp. 627-631, November 2007 (acceptance rate 27.3%).

 

[C45] [ICCAD’07] *Wei Dong, *Zhuo Feng and Peng Li, “Efficient VCO phase macromodel generation considering statistical parametric variations,” in Proc. of IEEE/ACM Int. Conf. on Computer-Aided Design, pp. 874-878, November 2007 (acceptance rate 27.3%).

 

[C44] [ICCAD’07] Yang Yi, Peng Li, Vivek Sarin and Weiping Shi, “Impedance extraction for 3-D structures with multiple dielectrics using preconditioned boundary element method”, in Proc. of IEEE/ACM Int. Conf. on Computer-Aided Design, pp. 7-10, November 2007 (acceptance rate 27.3%).

 

[C43] [ICCAD’07]*Guo Yu and Peng Li, “Yield-aware analog integrated circuit optimization using Geostatistics motivated performance modeling,” in Proc. of IEEE/ACM Int. Conf. on Computer-Aided Design, pp. 464-469, November 2007, (acceptance rate 27.3%).

 

[C42] [ITC’07] *Guo Yu and Peng Li, “A methodology for systematic built-in self-test of phase-locked loops targeting at parametric failures,” pp. 1-10, in Proc. of IEEE Int. Test Conference, October 2007.

 

[C41] [BMAS’07] Garng M. Huang, *Wei Dong, Yenpo Ho, and Peng Li, “Tracing SRAM separatrix for dynamic noise margin analysis under device mismatch,” in Proc. of IEEE Int. Behavioral Modeling and Simulation Conf., pp. 6-10, September 2007.

 

[C40] [CICC’07] *Wei Dong, Peng Li and *Xiaoji Ye, “Efficient frequency-domain simulation of massive clock meshes using parallel harmonic balance,” in Proc. of IEEE Custom Integrated Circuits Conference, pp. 631-634, September 2007 (acceptance rate 48.2%).

 

[C39] [DAC’07] *Xiaoji Ye, Yaping Zhan and Peng Li, “Statistical leakage power minimization using fast equi-slack shell based optimization,” in Proc. of IEEE/ACM Design Automation Conference, pp. 853-858, June 2007 (acceptance rate 23.2%).

 

[C38] [DAC’07] *Guo Yu, *Wei Dong, *Zhuo Feng and Peng Li, “A framework for accounting for process model uncertainty in statistical static timing analysis,” in Proc. of IEEE/ACM Design Automation Conference,  pp. 829-834, June 2007 (acceptance rate 23.2%).

 

[C37] [DAC’07] *Wei Dong and Peng Li, “Accelerating harmonic balance simulation using efficient parallelizable hierarchical preconditioning,” in Proc. of IEEE/ACM Design Automation Conference, pp. 436-439, June 2007 (acceptance rate 23.2%).

 

[C36] [DAC07] *Zhuo Feng, Peng Li and Yaping Zhan, “Fast second-order statistical static timing analysis using parameter dimension reduction,” in Proc. of IEEE/ACM Design Automation Conference, pp. 244-249, June 2007 (acceptance rate 23.2%).

 

[C35] [ISQED’07] *Guo Yu, Peng Li and *Wei Dong, “Achieving low-cost linearity test and diagnosis of Sigma-Delta ADCs via frequency-domain nonlinear analysis and macromodeling”, in Proc. of IEEE Int. Symp. on Quality Electronic Design, pp. 513-518, March 2007 (acceptance rate 33%).

 

[C34] [ISQED’07] *Zhuo Feng, *Guo Yu and Peng Li, “Reducing the complexity of VLSI performance variation modeling via parameter dimension reduction”, in Proc. of IEEE Int. Symp. on Quality Electronic Design, pp. 737-742,  March 2007 (acceptance rate 33%).

 

[C33] [TAU’07] *Xiaoji Ye, Yaping Zhan and Peng Li, “Statistical leakage power minimization using fast equi-slack shell based optimization,” in Proc. of ACM/IEEE Int. Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, pp. 37-42, February 2007 (acceptance rate 44.0%).

 

[C32] [TAU’07] *Zhuo Feng and Peng Li, “Parameterized waveform-independent gate models for timing and noise analysis”, in Proc. of ACM/IEEE Int. Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, pp. 61-65, February 2007 (acceptance rate 44.0%).

 

[C31] [ICCAD’06] *Zhuo Feng and Peng Li, “Performance-oriented statistical parameter reduction of parameterized systems via reduced rank regression,” in Proc. of IEEE/ACM Int. Conf. on Computer-Aided Design, pp. 868-875, November 2006  (acceptance rate 23.4%) (Best paper award nomination, 16 out of 541 submissions, 3%).

 

[C30] [ICCAD’06] *Xiaoji Ye, Peng Li and Frank Liu, “Practical variation-aware interconnect delay and slew analysis for statistical timing verification”, in Proc. of IEEE/ACM Int. Conf. on Computer-Aided Design, pp. 54-59, November 2006 (acceptance rate 23.4%).

 

[C29] [ICCAD’06] Ganesh Venkataraman, *Zhuo Feng, Jiang Hu, Peng Li, “Combinatorial algorithms for fast clock mesh optimization,” in Proc. of IEEE/ACM Int. Conf. on Computer-Aided Design, pp. 563-567, November 2006 (acceptance rate 25.1%).

 

[C28] [EPEP’06] Yang Yi, Peng Li, Vivek Sarin, and Weiping Shi, “A preconditioned hierarchical algorithm for impedance extraction of interconnects in packages,” 15th IEEE Topical Meeting on Electrical Performance of Electronic Packaging (EPEP), pp. 99-102, October, 2006.

 

[C27] [DAC’06] *Guo Yu and Peng Li, “Lookup table based simulation and statistical modeling of Sigma-Delta ADCs”, in Proc. of IEEE/ACM Design Automation Conference, pp.1035-1040, July 2006 (acceptance rate 20.8%).

 

[C26] [DAC’06] Peng Li and Weiping Shi, “Model order reduction of linear networks with massive ports via frequency-dependent port packing,” in Proc. of IEEE/ACM Design Automation Conference, pp. 267-272, July 2006 (acceptance rate 20.8%).

 

[C25] [DAC’06] Shiyan Hu, Qiuyang Li, Jiang Hu and Peng Li, “Steiner network construction for timing critical nets,” in Proc. of IEEE/ACM Design Automation Conference, pp. 379-384, July 2006 (acceptance rate 20.8%).

 

[C24] [ISQED’06] *Zhuo Feng, Peng Li and Jiang Hu, “Efficient model update scheme for general link-insertion networks,” in Proc. of IEEE Int. Symp. on Quality Electronic Design, pp. 43-50,  March 2006 (acceptance rate 36.3%).

 

[C23] [ISQED’06] Peng Li, “Critical path analysis considering temperature, power supply variations and temperature induced leakage,” in Proc. of IEEE Int. Symp. on Quality Electronic Design, March 2006 (acceptance rate 36.3%).

 

[C22] [ICCAD’05] Peng Li, “Variational analysis of large power grids by exploring statistical sampling sharing and spatial locality,” in Proc. of IEEE/ACM Int. Conf. on Computer-Aided Design, pp. 645-651, November 2005 (acceptance rate 23.7%).

 

[C21] [ICCAD’05] Xin Li, Peng Li and Lawrence Pileggi, “Parameterized interconnect order reduction with explicit-and-implicit multi-parameter moment matching for inter/intra-die variations,” in Proc. of IEEE/ACM Int. Conf. on Computer-Aided Design, pp. 806-812, November 2005 (acceptance rate 23.7%).

 

[C20] [ICCAD’05] G. Venkataraman, N. Jayakumar, J. Hu, P. Li, S. Khatri, A. Rajaram, P. McGuinness and C. Alpert, “Practical techniques to reduce skew and its variations in buffered clock networks,” in Proc. of IEEE/ACM Int. Conf. on Computer-Aided Design, pp. 592-596, November 2005 (acceptance rate 23.7%).

 

[C19] [ICCD’05] Peng Li and Emrah Acar, “A waveform independent gate model for accurate timing analysis,” in Proc. of IEEE  Int. Conf. on Computer Design, pp. 363-365, October 2005 (acceptance rate 23.0%).

 

[C18] [ICCD’05] Peng Li, Yongdong Deng and Lawrence Pileggi, “Temperature-dependent optimization of cache leakage power dissipation,”  in Proc. of IEEE  Int. Conf. on Computer Design, pp. 7-12, October 2005 (acceptance rate 23.0%).

 

[C17] [CICC’05] Rohan Batra, Peng Li, Lawrence T. Pileggi and Wan-ju Chiang, "A behavioral level approach for nonlinear dynamic modeling of voltage-controlled oscillators," in Proc. of IEEE Custom Integrated Circuit Conference, pp. 717-720, September 2005 (acceptance rate 26.3%).

 

[C16] [DAC’05] Peng Li, "Power grid simulation via efficient sampling-based sensitivity analysis and hierarchical symbolic relaxation," in Proc. of IEEE/ACM Design Automation Conference), pp. 664-669, June 2005 (acceptance rate 21.0%).

 

[C15] [DATE’05] Peng Li, Frank Liu, Xin Li, Lawrence Pileggi and Sani Nassif, "Modeling interconnect variability using efficient parametric model order reduction," in Proc. of Design Automation and Test In Europe Conference (DATE), pp. 958-963, March 2005, (acceptance rate 21.3%).

 

[C14] [DATE’05] Sounil Biswas, Peng Li, Ronald D. Blanton and Lawrence T. Pileggi, "Specification test compaction for analog circuits and MEMS,” in Proc. of Design Automation and Test In Europe Conference (DATE), pp. 164-169 March 2005 (acceptance rate 21.3%).

 

[C13] [ICCAD’04] Peng Li, Lawrence Pileggi, Mehdi Asheghi and Rajit Chandra, “Efficient full-chip thermal modeling and analysis,” in Proc. of IEEE/ACM Int. Conf. on Computer-Aided Design (ICCAD), pp. 319-326, November 2004 (acceptance rate 24.4%).

 

[C12] [ICCAD’04] Peng Li and Lawrence Pileggi, “Efficient harmonic balance simulation using multi-level frequency decomposition,” in Proc. IEEE/ACM Int. Conf. on Computer-Aided Design (ICCAD), pp. 677-682, November 2004 (acceptance rate 24.4%),
(Best paper award nomination).

 

[C11] [BMAS’04] Rohan Batra, Peng Li, Lawrence Pileggi and Yu-Tsun Chien, "A methodology for analog circuit macromodeling," in Proc. of IEEE International Behavioral Modeling and Simulation Conference, pp. 41- 46, October 2004.

 

[C10] [DAC’04] Xin Li, Yang Xu, Peng Li, Padmini Gopalakrishnan and Lawrence Pileggi, “A frequency relaxation approach for analog/RF system-Level simulation,” in IEEE/ACM Design Automation Conf. , pp. 842-847, June 2004, (acceptance rate 20.8%).

 

[C9] [BMAS’03] Peng Li  and Lawrence Pileggi, “Modeling nonlinear communication ICs using a multivariate formulation,” in Proc. of  IEEE International Workshop on Behavioral Modeling and Simulation, pp. 24-27, October 2003.

 

[C8] [ICCAD’03] Peng Li, Xin Li, Yang Xu and Lawrence Pileggi, “A hybrid approach to nonlinear macromodel generation for time-varying analog circuits,” in Proc. IEEE/ACM Int. Conf. on Computer-Aided Design, pp. 454-461, November 2003 (acceptance rate 26.3%).

 

[C7] [DAC’03] Peng Li and Lawrence Pileggi, “NORM: compact model order reduction of weakly nonlinear systems,” in Proc. of 40th IEEE/ACM Design Automation Conference, pp. 472-477, June 2003, (acceptance rate 24.2%) 
(Best Paper Award, four out of 628 submissions, 0.6%).

 

[C6] [DAC’03] Xin Li, Peng Li, Yang Xu and Lawrence Pileggi, “Analog and RF circuit macromodels for system-level analysis,” in Proc. of 40th IEEE/ACM Design Automation Conference (DAC), pp. 478-483, June 2003, (acceptance rate 24.2%).

 

[C5] [DATE’03] Yang Xu, Xin Li, Peng Li and Lawrence Pileggi, “Noise macromodel for radio frequency integrated circuits,” in Proc. of IEEE/ACM Design Automation & Test In Europe Conference (DATE),  pp. 150-155, March 2003 (acceptance rate 25.8%).

 

[C4] [ASP-DAC’03] Peng Li and Lawrence Pileggi, “Nonlinear distortion analysis via linear-centric models,” in Proc. of IEEE/ACM Asia and South Pacific Design Automation Conf., pp. 897-903, January 2003, (acceptance rate 33.6%).

 

[C3] [ASP-DAC’03] Xin Li, Peng Li, Yang Xu, Robert Dimaggio and Lawrence Pileggi, “A frequency separation macromodel for system-level simulation of RF circuits,” in Proc. of IEEE/ACM Asia and South Pacific Design Automation Conf., pp. 891-896, January, 2003 (acceptance rate 33.6%).

 

[C2] [DATE’02] Peng Li and Lawrence Pileggi, “A linear-centric approach to harmonic balance analysis,” in Proc. of IEEE/ACM Design Automation & Test In Europe Conf., pp. 634-639, March 2002 (acceptance rate 29.8%).

 

[C1] [SLIP’00] Peng Li, Pranab K. Nag and Wojciech Maly, “Cost based tradeoff analysis of standard cell designs,” in Proc. of ACM International Workshop on System-Level Interconnect Prediction, pp. 129-135, April 2000.

   

Book Chapters

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[B6] Peng Li, *Wei Dong and Garng M. Huang, “Dynamic stability of static memories: concepts and advanced numerical analysis techniques,” 19 pages, in Simulation and Verification of Electronic and Biological Systems (book title, editors: Peng Li, L. Miguel Silveira and Peter Feldmann), Springer, 2011.

 

[B5] Peng Li and Wei Dong, “Parallel preconditioned hierarchical harmonic balance for analog and RF circuit simulation,” 20 pages, pp. 111-130, in Advances in Analog Circuits, IN-TECH Press (http://www.intechweb.org), ISBN 978-953-307-323-1, February 2011.

 

[B4] Esteban Tlelo-Cuautle, Elyoenai Martínez-Romero, Carlos Sánchez-López, Francisco V. Fernández, Sheldon X.-D. Tan, Peng Li and Mourad Fakhfakh, “Behavioral modeling of mixed-mode integrated circuits,” pp.85-108, in Advances in Analog Circuits (book title), IN-TECH Press (http://www.intechweb.org), ISBN 978-953-307-323-1, February 2011.

 

[B3]  Rasit Onur Topaloglu, *Zhuo Feng and Peng Li, “Interconnect variability and performance analysis,” 18 pages, in Recent Topics on Modeling of Semiconductor Processes, Devices and Circuits (editor: Rasit Onur Topaloglu, co-editor: Peng Li), Bentham Publishing (www.ebook-engineering.org) 2009 (in press).

 

[B2]  Rasit Onur Topaloglu, *Guo Yu and Peng Li, “Probability propagation and yield optimization for analog circuits,” 19 pages, in Recent Topics on Modeling of Semiconductor Processes, Devices and Circuits (editor: Rasit Onur Topaloglu, co-editor: Peng Li), Bentham Publishing (www.ebook-engineering.org) 2009 (in press).

 

[B1] *Guo Yu and Peng Li, “Robust design and test of analog/mixed-signal circuits in deeply scaled CMOS technologies", pp. 353-374, in VLSI (book title), IN-TECH Press (http://www.intechweb.org/), ISBN 978-953-307-049-0, February 2010.

   

Others

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[O6] [TECHCON0’11] *Zhiyu Zeng, *Suming Lai and Peng Li, “IC power delivery: voltage regulation, conversion and system-level co-optimization,” SRC TECHCON, 4 pages, September 2011.

 

[O5] [TECHCON0’10] *Leyi Yin and Peng Li, “In-situ jitter test and diagnosis of digital PLLs using digital reconfiguration,” SRC TECHCON, 4 pages, September 2010.

 

[O4] [TECHCON0’10] *Zhiyu Zeng, Zhuo Feng and Peng Li, “Tradeoff analysis and optimization of power delivery networks with on-chip voltage regulation,” SRC TECHCON, 4 pages, September 2010.

 

[O3] [TECHCON’09] *Xioaji Ye, Wei Dong and Peng Li, “A hierarchical multi-Algorithm parallel circuit simulation framework,” SRC TECHCON, 4 pages, September 2009 (Best in Session Award).

 

[O2] [TECHCON’09] *Guo Yu and Peng Li, “Hierarchical synthesis of large mixed-signal circuits with consideration of process variations,” SRC TECHCON, 4 pages, November 2009.

 

[O1] [TECHCON’08] *Zhuo Feng, Peng Li and Zhuoxiang Ren, “Design-dependent statistical interconnect corner extraction under inter/intra-die variations,” SRC TECHCON, 4 pages, November 2008.