System-Theoretic Analysis and Design for Dynamic Stability of Memory Devices in Nanoscale CMOS and Beyond



Peng Li


Garng M. Huang


National Science Foundation (NSF)

Directorate for Computer & Information Science & Engineering (CSE)

Division of Computer and Communication Foundations (CCF)

NSF Award #:



August 1, 2009 – July 31, 2012

NSF Project Site:




Data storage is essential to a broad range of electronic and biological systems. Static random access memories (SRAMs) provide essential on-chip data storage for many electronic applications including microprocessors, ASICs, DSPs and SoCs. There also exists a growing effort in developing engineered genetic memory circuits to facilitate new understanding of cellular phenomena in natural organisms, cellular control and biocomputing. This work intends to facilitate the understanding, analysis and enhancement of dynamic stability, a key system property, for semiconductor SRAMs, emerging memristor and biological memories. Conventional static SRAM stability metrics are unable to capture intrinsic dynamic circuit operations and hence inherently limited in their applications. This work addresses the need for a rigorous understanding of dynamic stability in semiconductor and genetic memories via a system-theoretic approach. Nonlinear system theory will be exploited to construct new dynamic noise margin concepts and design metrics with theoretic rigor and design insights. Novel system theoretically motivated numerical algorithms will be developed to facilitate analysis and optimization with significantly improved efficiency.

This work will facilitate the design of nanoscale computing systems as well as the development of synthetic gene-regulatory networks. Interdisciplinary explorations will provide new opportunities for solving research problems of practical significance and offer educational opportunities to students. The PIs will promote the research participation from undergraduate students and students from underrepresented groups and engage in high-school teacher enrichment programs. The research outcomes will be integrated into undergraduate and graduate curriculum and disseminated in the research community and major semiconductor companies. 


Research Highlights 

New SRAM Dynamic Noise Margin Concepts and System-theoretical Characterization

Technology scaling in sub-100nm regime has signicantly shrunk the SRAM stability margins in data retention, read and write. Conventional static noise margins (SNMs) are unable to capture nonlinear cell dynamics and become inappropriate for state-of-the-art SRAMs with shrinking access time and/or advanced dynamic read-write-assist circuits. Using the insights gained from rigorous nonlinear system theory, we define the much needed SRAM dynamic noise margins (DNMs) based on the notation of stability boundary, or separatrix, as illustrated in the 2D state space below:


The importance of the separatrix lies in the facts: 1) it separates the two stable equilibria in the state space, and 2) it facilitates a precise characterization of state flips, hence the stability of the cell, in the desirable dynamic fashion. As such, we define new DNM metrics read, write and hold in terms of wordline pulse width and/or separatrix crossing time. The new read DNM  is illustrated below [Dong, Li and Huang, ICCAD’08]:


The DNMs not only capture key SRAM nonlinear dynamical characteristics, they also provide valuable design insights. These new DNM metrics have significant advantages over their static noise margin (SNM) counterparts. For example, the inherent pessimism in read SNM and optimism in write DNM are eliminated.

Furthermore, we apply rigorous system theory can be exploited to develop CAD algorithms that can analyze SRAM dynamic stability characteristics up to three orders of magnitude faster than brute-force approaches while maintaining SPICE-level accuracy. Using our system-theoretical fast separatrix characterization algorithm as a basis, we further develop a parametric dynamic stability analysis approach suitable for low-probability cell failures, leading to up to five orders of magnitude runtime speedup for yield analysis under high-sigma parameter variations. In the 2D state space, the separatrix can efficiently traced using only two transient runs on a modified circuit, an approach that is much faster than brute-force state space sampling [Huang, Dong, Ho and Li, BMAS’07] [Dong, Li and Huang, ICCAD’08], as illustrated below:


The same approach can be extended to high-dimensional state spaces (e.g. for memory cells with fully extracted parasitics). However, tracing the separatrix in a high-dimensional state space becomes cumbersome. This difficulty is addressed by efficiently computing the tangent to the separatrix and using it as a basis for fast and approximate DNM analysis. Fast iterative refinement can be further introduced to provide exact DMN values in high-dimensional state spaces [Zhang, Li and Huang, DAC’10].


Device Characteristics and Design Implications of Nonvolatile Memristor Memories

The search for new nonvolatile universal memories is propelled by the need for pushing power-efficient nanocomputing to the next higher level. As a potential contender for the next-generation memory technology of choice, the recently found “the missing fourth circuit element”, memristor, has drawn a great deal of research interests. As an emerging device, memristors have a very unique set of device characteristics, which have not been fully analyzed, particularly from a design point of view. We start from the reported very basic memristor device models and derive a set of closed-form design equations. Our design equations succinctly capture the memristor behaviors in a way relevant to memory operations and provide clear design insights. By utilizing the design guidance derived from our closed-form expressions, we propose suitable memory read and write schemes. We investigate the unique circuit design, noise margin and data integrity issues arisen from the fundamental memristor device characteristics. We develop in-depth analysis and suggest circuit design solutions to achieve reliable read and write operations [Ho, Huang and Li, ICCAD’09].  The basic memristor device structure and the investigated read/write circuitry are illustrated below:


The dynamic characteristics of memristor devices impose unique design considerations so as to facilitate proper read and write operations and guarantee stability. As an example, the read input signal pattern must be properly designed to avoid disruptive reads. As shown in the following picture, the read signal pattern consists of a negative pulse followed with a positive pulse with equal pulse width. The mismatch between two pulse widths and its impact on read stability need to be assessed and proper refresh schemes may be needed to restore the data.



Related Publications 


Note: Supervised students are delineated with an asterisk (*).


[DAC10] *Yong Zhang, Peng Li and Garng M. Huang, “Separatrices in high-dimensional state space: system-theoretical tangent computation and application to SRAM dynamic stability analysis,” in Proc. of ACM/IEEE Design Automation Conf., June 2010 (acceptance rate 24.4%).


[JLPE10] *Akshit Dayal, Peng Li and Garng M. Huang, “Robust SRAM design via joint sizing and voltage optimization under dynamic stability constraints,” in Journal of Low Power Electronics, vol. 6, no. 1, Apr. 2010.


[ICCAD09] *Yenpo Ho, Garng M. Huang and Peng Li, “Nonvolatile memristor memory: device characteristics and design implications,” in Proc. of IEEE/ACM Int. Conf. on Computer-Aided Design, pp. 485-490, November 2009 (acceptance rate 26.3%).


[ICCAD09] *Yong Zhang and Peng Li, “Gene-regulatory memories: electrical-equivalent modeling, simulation and parameter identification,” in Proc. of IEEE/ACM Int. Conf. on Computer-Aided Design, pp. 491-496, November 2009 (acceptance rate 26.3%).


[ICCAD08] *Wei Dong, Peng Li and Garng M. Huang, “SRAM dynamic stability: theory, variability and analysis,” in Proc. of IEEE/ACM Int. Conf. on Computer-Aided Design, pp. 378-385, November 2008 (acceptance rate 26.6%) (Best paper award nomination, 14 out of 458 submissions, 3%).


[BMAS07] Garng M. Huang, *Wei Dong, *Yenpo Ho, and Peng Li, “Tracing SRAM separatrix  for dynamic noise margin analysis under device mismatch,” in Proc. of IEEE Int. Behavioral Modeling and Simulation Conf., pp. 6-10, September 2007. 



Acknowledgement and Disclaimer 


This material is based upon work supported by the National Science Foundation under Grant No. 0917204.

Any opinions, findings, and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the National Science Foundation.


 Copyright by Peng Li.