Publications

	Citation	PDF
	H. Qian, Q. Liu, J. Silva-Martinez, S. Hoyos, “A 35 dBm Output Power and 38 dB Linear Gain PA With 44.9% Peak PAE at 1.9 GHz in 40 nm CMOS,” IEEE Journal of Solid State, Vol. 51, Issue 3, pp. 587-597, March 2016.
	A. Shafik, E. Zhian Tabasy, S. Cai, K. Lee, S. Hoyos, S. Palermo, “A 10 Gb/s Hybrid ADC-Based Receiver With Embedded Analog and Per-Symbol Dynamically Enabled Digital Equalization,” IEEE Journal of Solid State, Vol. 51, Issue 3, pp. 671 - 685, March 2016.
	H-J Jeon, J. Silva-Martinez, and S. Hoyos, “A Process-Variation-Resilient Current Mode Logic with Simultaneous Regulations for Time-constant, Voltage Swing, Level-shifting and DC gain by Using Time-Reference-Based Adaptive Biasing Chain,” IEEE Transactions on Very Large Scale Integration Systems, Vol. 23, No. 1, pp. 198-207 Jan. 2015.
	B. M. Sadler and S. Hoyos, “Towards a Standard Mixed-Signal Parallel Processing Architecture for Miniature and Microrobotics,” Journal of Research of the National Institute of Standards and Technology, Volume 119 (2014) http://dx.doi.org/10.6028/jres.119.020.
	E. Z. Tabasy, A. Shafik, K. Lee, S. Hoyos, S. Palermo, “A 6-bit 10-GS/s TI-SAR ADC with Low-Overhead Embedded FFE/DFE Equalization for Wireline Receiver Applications,” IEEE Journal of Solid State, Vol. 49, No. 11, pp. 2560-2574, Nov. 2014..
	J. Zhou, S. Hoyos, and B. M. Sadler, “Asynchronous Compressed Beamformer for Portable Diagnostic Ultrasound Systems,” IEEE Trans. on Ultrasonics, Ferroelectrics, and Frequency Control, Vol. 61, No. 11, pp. 1791-1801, Nov. 2014.
	H-J Jeon, J. Silva-Martinez, and S. Hoyos, “A Process-Variation-Resilient Current Mode Logic with Simultaneous Regulations for Time-constant, Voltage Swing, Level-shifting and DC gain by Using Time-Reference-Based Adaptive Biasing Chain,” IEEE Transactions on Very Large Scale Integration Systems, Vol. PP, Issue 99, pp. 1-5 Feb. 2014.
	E. Z. Tabasy, A. Shafik, S. Huang, N.H.-W. Yang, S. Hoyos, S. Palermo, “A 6b 1.6GS/s ADC with Redundant Cycle One-Tap Embedded DFE in 90nm CMOS,” IEEE Journal of Solid State, Vol. 48, No. 8, pp. 1885-1897, Aug. 2013.
	X. Chen, E.A. Sobhy, Z. Yu, S. Hoyos, J. Silva-Martinez, S. Palermo, and B.M. Sadler, “A Sub-Nyquist Rate Compressive Sensing Data Acquisition Front-end,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol. 2, No. 3, pp. 482-492, Sept. 2012.
	J. Zhou, M. Ramirez, S. Palermo, S. Hoyos, “Digital-Assisted Asynchronous Compressive Sensing Front-End,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol. 2, No. 3, pp. 542-551, Sept. 2012.
	R. Ahmed, D.L. Aristizabal-Ramirez, and S. Hoyos, “Sensitivity Analysis of Continuous-Time Delta-Sigma ADCs to Out-of-Band Blockers in Future SAW-Less Multi-Standard Wireless Receivers,” IEEE Transactions on Circuits and Systems I, Vol. 59, No. 9, pp. 1894-1905, Sept. 2012.
	Z. Yu, J. Zhou, M. Ramirez, S. Hoyos, B.M. Sadler, “The impact of ADC nonlinearity in a mixed-signal compressive sensing system for frequency-domain sparse signals,” Physical Communication, 17 November 2011, ISSN 1874-4907, 10.1016/j.phycom.2011.10.007.
	S. Hoyos, B. Tsang, J. Vanderhaegen, Y. Chui, Y. Aibara, H. Khorramabadi, and B. Nikolic, “A 15 MHz to 600 MHz, 20 mW, 0.38 mm2 Split-Control, Fast Coarse Locking Digital DLL in 0.13um CMOS,” IEEE Transactions on Very Large Scale Integration Systems, Vol 20, Num 3, pp. 1-5, Mar. 2012.
	S. Pentakota, M. Ramirez, and S. Hoyos, “Least Mean Squared Background Calibration For OFDM Multi Channel Receivers,” Journal of Circuits, Systems, and Computers, Volume 21, Issue 01, February 2012.
	E. A. Sobhy, A. Helmy*, S. Hoyos, K. Entesari and E. Sánchez-Sinencio, “A 2.8 mW Sub-2 dB Noise Figure Inductorless Wideband CMOS LNA Employing Multiple Feedback,” IEEE Transactions on Microwave Theory and Techniques, Vol. 59, pp. 3154 - 3161, Issue 12, Dec. 2011.
	E. A. Sobhy, S. Pentakota, Z. Yu, and S. Hoyos “Analytical Framework and Bandwidth Optimization of OFDM Low-Order Multi-Channel Filter-Bank Receivers for Achieving Sampling Clock-Jitter-Robustness,” IET Circuits Devices Syst. -- September 2011 -- Volume 5, Issue 5, p.360–364. ISSN: 1751-858X
	X. Chen, Z. Yu, S. Hoyos, B. M. Sadler, and J. Silva-Martinez, “A Sub-Nyquist Rate Sampling Receiver Exploiting Compressive Sensing,” IEEE Transactions on Circuits and Systems I, Vol. 58, Issue 3, pp. 507-520, Mar. 2011. Top ten most accessed paper of the TCAS Part-I, Feb 2011; top 16 most accessed paper, March 2011; top 17 most accessed paper, April 2011.
	S. Hoyos, S. Pentakota, Z. Yu, E. Sobhy, X. Chen, R. Saad, S. Palermo, and J. Silva-Martinez, “Clock-Jitter Tolerant Wideband Receivers: An Optimized Multi-Channel Filter-Bank Approach,” IEEE Transactions on Circuits and Systems I, Vol. 58, No. 2, pp. 253 – 263, Feb. 2011. Top nine most accessed paper of the TCAS Part-I, Feb 2011.
	R. Saad and S. Hoyos, "Feed-Forward Spectral Shaping Technique for Clock-Jitter Induced Errors in Digital-to-Analog Converters," IET Electronics Letters, Vol 47, Issue 3, pp. 826-828, Feb. 2011.
	E.A. Sobhy and S. Hoyos, “A Multiphase Multipath Technique With Digital Phase Shifters for Harmonic Distortion Cancellation,” IEEE Transactions on Circuits and Systems II, Vol. 57 , No. 12, pp. 921-925, Dec. 2010.
	R. Saad and S. Hoyos, "Sensitivity of single-bit continuous-time analogue-to-digital converters to out-of-band blockers," IET Electronics Letters, Vol. 46, No. 12, pp. 826–828, June 2010.
	K. Raviprakash, R. Saad, and S. Hoyos, “Reduced Area Discrete-Time Down-Sampling Filter Embedded with Windowed Integration Samplers,” IET Electronics Letters, Vol. 46, Issue 12, pp. 828–830, June 2010.
	J. Kim, S. Hoyos, and J. Silva-Martinez, “Wideband Common-Gate CMOS LNA Employing Dual Negative Feedback with Simultaneous Noise, Gain, and Bandwidth Optimization,” IEEE Transactions On Microwave Theory And Techniques, Vol. 58, No. 9, pp. 2340-2351, Sept. 2010. Top 2 most read paper of the IEEE- Microwave Theory and Techniques, September 2010.
	C.-Y. Lu, F. Silva-Rivas, P. Kode, J. Silva-Martinez, and S. Hoyos, "A 6th-order 200MHz IF Bandpass Sigma-Delta Modulator With over 68dB SNDR in 10MHz Bandwidth,” IEEE Journal of Solid State Circuits, Vol. 45, No. 6, pp. 1122-1136, June 2010. Top 16 most accessed paper in IEEE overall, June 2010, and top 6 most read paper of the IEEE- Journal of Solid-State Circuits, June 2010.
	E. A. Sobhy, S. Hoyos, and E. Sánchez-Sinencio, "High-PSRR Low-Power Single Supply OTA," IEE Electronics Letters, Vol. 46, Issue 5, pp. 337 – 338, March 2010.
	Z. Yu, X. Chen, S. Hoyos, B. M. Sadler, J. Gong, and C. Qian, "Mixed-Signal Parallel Compressive Spectrum Sensing for Cognitive Radios," International Journal of Digital Multimedia Broadcasting, Vol. 2010, 10 pages, Jan. 2010.
	K. Raviprakash, M. Kulkarni, X. Chen, S. Hoyos, and B. M. Sadler, “A Discrete-Time Downsampling FIR Filter for Windowed Integration Samplers,” International Journal of Microwave Science and Technology, vol. 2009, Article ID 758783, 10 pages, 2009. doi:10.1155/2009/758783.
	P. Kotte, M. Kulkarni, X. Chen, Z. Yu, S. Hoyos, J. Silva-Martinez, and E. Sanchez-Sinencio, “Applications of Multi-Path Transform-Domain Charge-Sampling Wideband Receivers,” IEEE Transactions on Circuits and Systems , Vol. 55, No. 4, pp. 309-313, April 2008.
	S. Hoyos and B.M. Sadler, “UWB mixed-signal transform-domain direct-sequence receiver,” IEEE Transactions on Wireless Communications, Vol. 6, No. 8, pp. 3038-3046, Aug. 2007.
	S. Hoyos and B. M. Sadler, “Frequency-Domain Implementation of the Transmitted-Reference Ultra-Wideband Receiver,” IEEE Transactions On Microwave Theory and Techniques, Vol. 54, Issue 4, Part 2, pp. 1745 – 1753, April 2006.
	S. Hoyos, B. M. Sadler, and G. R. Arce, “Broadband Multicarrier Communications Receiver Based on Analog to Digital Conversion in the Frequency Domain,” IEEE Transactions on Wireless Communications, Vol. 5, Issue 3, pp. 652 – 661, March 2006.
	S. Hoyos and B. M. Sadler, “Ultra-wideband analog to digital conversion via signal expansion,” IEEE Transactions on Vehicular Technology, Vol. 54, No. 5, pp. 1609-1622, Sept. 2005. Invited.
	S. Hoyos, B. M. Sadler, and G. R. Arce, “Mono-bit digital receivers for ultra-wideband communications,” IEEE Transactions Letters on Wireless Communications, Vol. 4, No. 4, pp.1337-1344, July 2005. Top 5% (170/3598) most cited paper in this journal history.
	S. Hoyos, J. Bacca, and G. R. Arce, “Spectral design of weighted median filters: A general iterative approach,” IEEE Transactions on Signal Processing, Vol. 53, Issue 3, pp:1045 – 1056, March 2005.
	S. Hoyos, Y. Li, J. Bacca, and G. R. Arce, “Weighted median filters admitting complex-valued weights and their optimization,” IEEE Transactions on Signal Processing, Vol. 52, Issue 10, pp. 2776 – 2787, Oct. 2004.
	S. Hoyos, J. A. Garcia, and G. R. Arce, “Mixed-signal equalization architectures for printed circuit boards,” IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 51, num. 2, pp. 264-274, Feb. 2004.

Book Chapters

	Citation	PDF
	J. Silva-Martinez, F. Silva-Rivas, C-Y. Lu, J. Mincey and S. Hoyos, “Digitally-Based Calibration Techniques for RF Sigma-Delta Modulators,” chapter in Design, Modeling and Testing of Data Converters, Signals and Communication Technology, DOI: 10.1007/978-3-642-39655-7_4, Springer-Verlag Berlin Heidelberg 2014.
	R. Saad, S. Hoyos and S. Palermo, “Analysis and Modeling of Clock-Jitter Effects in Delta-Sigma Modulators,” book chapter in “MATLAB - A Fundamental Tool for Scientific Computing and Engineering Applications - Volume 1” edited by Vasilios N. Katsikis, ISBN 978-953-51-0750-7, Publisher: InTech, September 26, 2012.
	J. Silva-Martinez, S. Hoyos, C-Y Lu, M. Onabajo, and F. Silva-Rivas*, “Broadband High-Resolution Bandpass Sigma-Delta Modulator With a Software Based Calibration Scheme,” book Chapter in “Circuits for Emerging Technologies”, edited by Kris Iniewski. CRC Press, June 2011.
	S. Hoyos, “Multi-Mode/Multi-Band RF Transceivers for Wireless Communications Advanced Techniques, Architectures, and Trends. Chapter7: Transform Domain Receivers for Multi-Standard Communications”, Wiley, 2011.
	S. Hoyos and B. M. Sadler, “Ultra-Wideband Wireless Communications and Networks, Chapter 6: Mixed Signal UWB Communications Receivers”, Wiley, 2006.

Patents

	Citation
	R. Ahmed, S. Hoyos, and J. Silva-Martinez, “Jitter Cancellation Method for Continuous-Time Sigma-Delta Modulators,” Patent No.: US 8164500, April 24, 2012.
	S. Hoyos, B. M. Sadler, and G. R. Arce, “Analog to digital conversion with signal expansion,” Patent No.: US 7253761 B1, Aug. 7, 2007.

Online Courses

	Citation
	S. Hoyos, “Multi-Path Receivers Architectures for Wideband Multi-Standard Radios,” Online course in IEEE Education and Learning, offered since 2010.

Conference Papers

	Citation	PDF
	A. Shafik, E. Zhian Tabasy, S. Cai, K. Lee, S. Hoyos, and S. Palermo, “A 10Gb/s hybrid AC-based receiver with embedded 3-tap FFE and dynamically-enabled digital equalization in 65nm CMOS,” to appear in ISSCC Dig. Tech. Papers, Feb. 2015.
	J. Zhou and S. Hoyos, “Asynchronous Compressive Multi-Channel Radar for Interference-Robust Vehicle Collision Avoidance Systems,” IEEE Texas Symposium on Wireless and Microwave Circuits and Systems, Apr. 3-4, 2014, Waco, TX.
	J. Zhou, S. Palermo, J. Silva-Martínez, Brian M. Sadler, S. Hoyos, “Asynchronous Compressive Radar,” the 39th Annual Government Microcircuit Applications & Critical Technology Conference (GOMACTech)”, Mar. 31 - April 3, 2014, Charleston, SC.
	E. Zhian Tabasy, A. Shafik, K. Lee, S. Hoyos, and S. Palermo, “A 6b 10GS/s TI-SAR ADC with embedded 2-tap FFE/1-tap DFE in 65nm CMOS,” IEEE Symp. VLSI Circuits, Jun. 2013, pp. C274-C275
	J. Zhou, S. Palermo, B. M. Sadler, S. Hoyos, “Asynchronous Compressive Sensing in Radar Systems,” IEEE Texas Symposium on Wireless and Microwave Circuits and Systems, pp: 1 – 4, 2013.
	J. Zhou, Y. He, M. Chirala, B. M. Sadler, and S. Hoyos, “Compressed Digital Beamformer With Asynchronous Sampling For Ultrasound Imaging,” ICASSP 2013, May 26-31, Vancouver CA.
	E. Zhian Tabasy, A. Shafik, S. Huang, N. Yang, S. Hoyos, and S. Palermo, “A 6b 1.6GS/s ADC with Redundant Cycle 1-Tap Embedded DFE in 90nm CMOS,” IEEE Custom Integrated Circuits Conference, San Jose CA, Sep. 2012.
	R. Saad, E. A. Sobhy, and S. Hoyos, “A 384-MHz Continuous-Time Delta-Sigma Modulator using a Hybrid Feedback DAC Based on Spectral Shaping of Jitter Induced Errors,” SRC TECHCON 2011, Austin TX. Best paper award.
	R. Saad, and S. Hoyos, “Sensitivity Analysis of Pulse-Width Jitter Induced Noise in Continuous-Time Delta-Sigma Modulators to Out-of-Band Blockers in Wireless Receivers,” IEEE International Symposium on Circuits and Systems (ISCAS 2011), May 2011, Rio de Janeiro, Brazil, pp. 1636 - 1639.
	R. Saad, S. Hoyos, and J. Silva-Martinez, “Hybrid Clock-Jitter Error Shaping Technique for Feedback Digital-to-Analog Converters (DACs) in Continuous-Time Sigma-Delta Modulators,” Proceedings of SRC TECHCON 2010, paper number 14.3, Sept. 2010.
	Z. Yu and S. Hoyos, “Compressive Spectrum Sensing Front-ends for Cognitive Radios,” Proceedings of IEEE International Conference on System, Man and Cybernetics (SMC), Oct. 11-14, San Antonio, TX, 2009 (invited paper)
	Z. Yu and S. Hoyos, “Digitally Assisted Analog Compressive Sensing,” IEEE Dallas Circuits and Systems Workshop (DCAS), Oct.4th -5th, 2009.
	S. Hoyos, “Compressive Spectrum Sensing for Cognitive Radios,” Proceeding of IEEE Colombian Chapter STSIVA 2009, Pereira, Colombia, Sept. 9-11. (Best paper award).
	Y.-C. Lo, H.-P. Chen, J. Silva-Martinez, and S. Hoyos, "A 1.8V, sub-mW, over 100% locking range, divide-by-3 and 7 complementary-injection-locked 4 GHz frequency divider," IEEE Custom Integrated Circuits Conference, pp. 259-262, Sep. 2009.
	X. Chen, J. Silva-Martinez, and S. Hoyos, “A CMOS Differential Noise Cancelling Low Noise Transconductance Amplifier,” Proceedings of DCAS 2008, Dallas Circuits and Systems Workshop, Dallas, TX, Oct. 19-20, 2008.
	C. W. Tsang, Y. Chiu, J. Vanderhaegen, S. Hoyos, C. Chen, R. Brodersen, and B. Nikolic, “Background ADC Calibration in Digital Domain,” Proceedings of 2008 IEEE Custom Integrated Circuits Conference (CICC), San Jose, CA, Sept. 21 - 24 , 2008.
	S. Hoyos, C. W. Tsang, J. Vanderhaegen, Y. Chiu, Y. Aibara, H. Khorramabadi, and B. Nikolić, “A 15 MHz – 600 MHz, 20 mW, 0.38 mm2, Fast Coarse Locking Digital DLL in 0.13um CMOS,” Proceedings of 34th European Solid-State Circuits Conference (ESSCC), Edinburgh, Sept. 15 – 19, 2008.
	Z. Wang, G. R. Arce, B. M. Sadler, J. L. Paredes, S. Hoyos and Z. Yu, "Compressed UWB Signal Detection with Narrowband Interference Mitigation," in Proc. IEEE ICUWB, Hannover, Germany, Sept. 2008.
	Z. Yu, S. Hoyos, and B. M. Sadler, “Mixed-Signal Parallel Compressed Sensing And Reception For Cognitive Radio,” Proceedings of ICASSP 2008, International Conference on Acoustics, Speech and Signal Processing, Las Vegas, NV, 2008.
	P. Kotte Prakasam, M. Kulkarni, X. Chen, S. Hoyos, and B. M. Sadler, “Emerging Technologies in Software defined receivers,” Proceedings of the IEEE Radio and Wireless Symposium, January 22-24, Orlando, FL, 2008.
	S. Hoyos and B. M. Sadler, “UWB mixed-signal transform-domain receiver front-end architectures,” The 6th IEEE Workshop on Signal Processing Advances in Wireless Communications, June 5- 8, New York City, 2005
	S. Hoyos, B. M. Sadler, and G. R. Arce, “Ultra-wideband multicarrier communication receiver based on analog to digital conversion in the frequency domain,” Proceedings of the IEEE Wireless Communications & Networking Conference (WCNCN), March 13-17, New Orleans, LA, 2005.
	S. Hoyos, B. M. Sadler, and G. R. Arce, “High-Speed A/D Conversion for Ultra-Wideband Signals Based on Signal Projection over Basis Functions,” Proceedings of ICASSP 2004, International Conference on Acoustics, Speech and Signal Processing, Montreal, Quebec, Canada, 2004.
	J. Bacca, S. Hoyos, Y. Li, and G. R. Arce, “Weighted Median Based Filters for the Complex Domain,” To appear in Proceedings of ICASSP 2004, International Conference on Acoustics, Speech and Signal Processing, Montreal, Quebec, Canada, 2004.
	S. Hoyos, B. M. Sadler, and G. R. Arce, “Intentional jamming suppression in a frequency-domain ultra-wideband multicarrier communication receiver,” Proceedings of the 24th Army Science Conference, Orlando, FL, Nov. 29, 2004
	S. Hoyos, B. M. Sadler, and G. R. Arce, “Analog to Digital Conversion of Ultra-Wideband Signals in Orthogonal Spaces,” Proceedings of IEEE Conference on Ultra Wideband Systems and Technologies (UWBST), Reston, VA, 2003.
	S. Hoyos, B. M. Sadler, and G. R. Arce, “Dithering and Sigma-Delta Modulation in Mono-bit Digital Receivers for Ultra-Wideband Communications,” Proceedings of IEEE Conference on Ultra Wideband Systems and Technologies (UWBST), Reston, VA, 2003.
	S. Hoyos, Y. Li, J. Bacca, and G. R. Arce, “Weighted median filters admitting complex-valued weights and their optimization,” Proceedings of IEEE-EURASIP Workshop on Nonlinear Signal and Image Processing (NSIP), Grado-Trieste, Italy, 2003.
	S. Hoyos, J. Bacca, and G. R. Arce, “Fast spectral design of weighted median filters admitting complex value weights,” Proceedings of IEEE-EURASIP Workshop on Nonlinear Signal and Image Processing (NSIP), Grado-Trieste, Italy, 2003.
	S. Hoyos, B. M. Sadler, and G. R. Arce, “On the performance of low complexity digital receivers for ultra-wideband communication systems,” Proceedings of Collaborative Technology Alliances (CTA) Annual Symposium, College Park, MD, 2003.
	S. Hoyos, J. Garcia, and G. R. Arce, “Mixed-signal equalization architectures for printed circuit boards,” Proceedings of International Conference on Acoustics, Speech and Signal Processing (ICASSP), Orlando, FL, 2002.

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Book Chapters

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Online Courses

Conference Papers